Implementation of JPEG 2000 MQ-Coder

JPEG 2000 has recently become one of the most rewarding image coding standards. It provides a practical set of features which weren´t necessarily available in the previous standards. The features were realized as a result of two new techniques, namely the discrete wavelet transform (DWT), and embedded block coding with optimized truncation (EBCOT). The complexity of EBCOT Tier-1 makes its hardware implementations very difficult. In this paper, we propose a new simplified architecture for the JPEG 2000 MQ-coder, as the primary section of EBCOT Tier 1. The design is for a complete EBCOT Tier-1 process, and considers system-level issues such as the need for buffering. Hardware architecture for the proposed process was developed, realized in VHDL, and synthesized for implementation on FPGA Xilinx.