A Digital Phase-locked Loop Based on MAP in PLC

The conventional DPLLs (digital phase-locked loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced class A noise model in PLC first, and then proposed an optimum DPLL for such class A noise environment using the techniques based on MAP (maximum a posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under class A noise environment.