A stability criterion for high-accuracy Δ-Σ digital resonators [ADC BIST applications]

The quick evolution of integrated circuit (IC) technologies towards complex system-on-chips (SoCs) architectures has been recently promoting many research efforts aimed at reducing test-related costs. In fact, actual measurement and testing expenses of high density, mixed-signal devices may cover almost 50% of the whole production budget. A well-known strategy to cope with these problems is built-in self-test (BIST), which relies on the integration of specific testing-oriented resources directly on chip. In particular, inexpensive, high-purity harmonic resonators are essential components for an accurate and fast characterization of the analog-to-digital converters (ADC) integrated in the same device. Δ-Σ harmonic resonators are apt to this purpose. Nevertheless, they have also proved to be critically stable and difficult to implement due to the lack of clear design criteria. This paper propose to fill this gap by presenting a general method to analyze the behavior of Δ-Σ resonators. thus suggesting useful guidelines for the implementation of more stable and robust schemes.