Location-Aware Cache-Coherence Protocols for Distributed Transactional Contention Management in Metric-Space Networks

A transactional memory API utilizes contention managers to guarantee that whenever two transactions have a conflict on a resource, one of them is aborted. While they have been well studied in the context of multiprocessors, their properties for distributed transactional memory systems are still unknown. Compared with multiprocessor transactional memory systems, the design of distributed transactional memory systems is more challenging because of the need for distributed cache-coherence protocols and the underlying (higher) network latencies involved. The choice of the combination of the contention manager and the cache-coherence protocol is critical for the performance of distributed transactional memory systems. How does a designer go about deciding what contention manager and what cache-coherence protocol to use in a distributed transactional memory system? In this paper, we answer this question. We consider metric-space networks, where the communication delay between nodes forms a metric. We show that the performance of a distributed transactional memory system on metric-space networks is O(N_i ²) for N_i transactions requesting for a single object under the Greedy contention manager and an arbitrary cache-coherence protocol. To improve the performance, we propose a class of location-aware distributed cache-coherence protocols, called LAC protocols. We show that the combination of the greedy contention manager and an efficient LAC protocol yields an O(N log N middot s) competitive ratio, where N is the maximum number of nodes that request the same object, and s is the number of objects. This is the first such performance bound established for distributed transactional memory contention managers. Our results yield the following design strategy: select a distributed contention manager and determine its performance without considering distributed cache-coherence protocols; then find an appropriate cache-coherence protocol to improve pe- rformance.