DocumentCode
1801809
Title
Implementation of High-speed High-resolution Data Conversion System Using FPGA
Author
Xiaoqiu, Cao ; Jin, Zeng ; Tao, Yang
Author_Institution
Beijing Univ. of Technol., Beijing
fYear
2007
fDate
Aug. 16 2007-July 18 2007
Abstract
This paper analyzes the implementation of high-speed high-resolution data conversion system based on Subranging A/D model in detail. We use a 10 bit ADC and an 8 bit ADC to construct the Subranging A/D system and then make a simulation by QuartusII. The result of the experiment shows that the system´s sampling rates is 17 MHz, and the resolution is 16 bit, so it can solve an antinomy between sampling rates and resolution, which is prevalent in current market.
Keywords
analogue-digital conversion; field programmable gate arrays; signal resolution; FPGA; QuartusII simulation; frequency 17 MHz; high-speed high-resolution data conversion system; sampling rates; sampling resolution; subranging A-D model; Consumer electronics; Control engineering; Data conversion; Educational institutions; Field programmable gate arrays; Instruments; Sampling methods; Signal processing; Signal resolution; Voltage; ADC; FPGA; High-resolution; High-speed;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Measurement and Instruments, 2007. ICEMI '07. 8th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4244-1136-8
Electronic_ISBN
978-1-4244-1136-8
Type
conf
DOI
10.1109/ICEMI.2007.4351279
Filename
4351279
Link To Document