A fast switching double processing architecture for multi-tasking real-time systems

A new fast switching double processing architecture for pipelined cache-based real-time computer systems is proposed to reduce the CPU stalls due to increased cache misses resulting from frequent task switching in multi-tasking real-time applications. In this architecture, two sets of registers are provided so that two tasks can be executed alternatively on a cycle-by-cycle basis. This architecture helps alleviate the problem of unpredictable cache performance due to frequent context switches in multi-tasking systems. The performance of the double processing is evaluated first through trace driven simulation for various cache configurations. An analytical performance model is then derived to further explain the performance advantage