DocumentCode
1801961
Title
Analysis and optimization of CMOS LNA noise performance with channel resistance
Author
Chen, Jiwei ; Shi, Bingxue
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Volume
3
fYear
2002
fDate
2002
Abstract
Channel resistance cannot be ignored when CMOS circuits operate at radio frequency (RF). Low noise amplifier (LNA) is a very important block in CMOS RF transceiver. The impact of channel resistance on the noise performance of LNA is thoroughly studied and analyzed, and new formulae are proposed systematically in this paper. Furthermore, revised noise figure optimization technique is presented. All of this work will be very instructive for the design of high performance LNA.
Keywords
CMOS analogue integrated circuits; MMIC amplifiers; circuit optimisation; field effect MMIC; integrated circuit noise; transceivers; CMOS; LNA; RF transceiver; channel resistance; noise figure optimization technique; noise performance; CMOS technology; Circuit noise; Cutoff frequency; Impedance matching; Inductors; Noise figure; Parasitic capacitance; Performance analysis; Radio frequency; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010281
Filename
1010281
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