Title :
Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 μm CMOS technologies
Author :
Sayed, Mohammed ; Badawy, Wael
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
This paper presents a performance analysis of single-bit full-adder cells using 0.18, 0.25, and 0.35 μm CMOS technology. Thirty-one single-bit full adder cells have been prototyped and simulated for power consumption, delay and charging capability. A comprehensive analysis is presented that studies the performance of the single-bit full adder cells using three different CMOS technologies.
Keywords :
CMOS logic circuits; adders; cellular arrays; digital arithmetic; 0.18 to 0.35 micron; CMOS technologies; charging capability; delay; power consumption; single-bit full adder cells; Adders; CMOS technology; Capacitors; Circuits; Delay; Energy consumption; Inverters; Performance analysis; Prototypes; Signal generators;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010285
