Area and power optimisation for AES encryption module implementation on FPGA

Author

Pham, Tuan Anh ; Hasan, Mohammad S. ; Yu, Hongnian

Author_Institution

Fac. of Comput., Eng. & Technol., Staffordshire Univ., Stafford, UK

fYear

2012

fDate

7-8 Sept. 2012

Firstpage

1

Lastpage

6

Abstract

Ubiquitous computing has been getting deployed into many applications in daily life. However, one of the difficulties to make it reliable is the lack of security. The constraints of area and power are the challenges for the cryptographic algorithms to be implemented. In this paper, the implementation of Advanced Encryption Standard (AES) encryption algorithm is proposed in terms of resource and power optimisation. The design is based on a 8-bit architecture and implemented on Altera Cyclone II EP2C672C6. The proposed design exhibits 272 LEs and takes 5.88 mW of power which is an improvement in comparison with other published works.

Keywords

cryptography; field programmable gate arrays; ubiquitous computing; AES encryption module implementation; Altera Cyclone II EP2C672C6; FPGA; advanced encryption standard; area optimisation; cryptographic algorithms; field programmable gate array; power 5.88 mW; power optimisation; resource optimisation; ubiquitous computing; word length 8 bit; Clocks; Computer architecture; Encryption; Field programmable gate arrays; Power demand; Random access memory; AES-128 encryption; FPGA; embedded system; resource-limited application;

fLanguage

English

Publisher

ieee

Conference_Titel

Automation and Computing (ICAC), 2012 18th International Conference on

Conference_Location

Loughborough

Print_ISBN

978-1-4673-1722-1

Type

conf

Filename

6330493