Title :
Noise-tolerant design and analysis for a low-voltage dynamic full adder cell
Author :
Fayed, Ayman A. ; Bayoumi, Magdy A.
Author_Institution :
The Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA, USA
Abstract :
In an attempt to study the behavior of dynamic circuits in the presence of deep submicron noise when operating at a low supply voltage, this paper presents noise tolerant design and analysis for an enhanced dynamic full adder cell based on the NORA-CMOS logic style. The noise tolerance capability is achieved by applying the twin-transistor technique on both the p and the n parts of the circuit. A prototype is constructed for both the standard and the designed noise tolerant circuits using 0.18 μm CMOS technology and simulated using HSPICE at supply voltage ranges from 0.9 V to 2.7 V. Noise immunity curves are developed and used to calculate the average noise threshold energy which shows a 2.5 times improvement when compared with the conventional design. The noise enhancement comes at the expense of 2.1 times extra power consumption.
Keywords :
CMOS logic circuits; SPICE; adders; integrated circuit design; integrated circuit modelling; integrated circuit noise; integrated circuit reliability; logic CAD; low-power electronics; 0.18 micron; 0.9 to 2.7 V; CMOS low-voltage dynamic full adder cell; HSPICE simulation; IC power consumption; NORA-CMOS logic style; average noise threshold energy improvement; deep submicron noise; noise analysis; noise enhancement; noise immunity curves; noise tolerance capability; noise tolerant design; supply voltage range; twin-transistor technique; Adders; CMOS logic circuits; CMOS technology; Circuit noise; Circuit simulation; Logic circuits; Logic design; Low voltage; Standards development; Virtual prototyping;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010290
