Hierarchical testing of VLSI systems based on device BIT

VLSI/VHSIC technology poses critical test problems not only at the device level, but also at the system level. The extreme functional complexity and fail-operational redundancy of VLSI systems tends to render conventional performance testing inadequate, not only in terms of failure mode coverage, but also in terms of test-time requirements. The authors propose a design structure in which various subsystems and modules using VLSI devices are related to one another in a hierarchical test scheme based on the reporting of individual, device-level built-in-test (BIT) results. This hierarchical approach offers true consistency between operational (in-flight), organizational, and depot-level test methodologies