Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme

Author

Sung, Kihyuk ; Yang, Byung-Do ; Kim, Lee-Sup

Author_Institution

Dept. of EECS, KAIST, Daejeon, South Korea

Volume

3

fYear

2002

fDate

2002

Firstpage

671

Lastpage

674

Abstract

A new interleaved synchronous mirror delay (SMD) is proposed in order to reduce the circuit size. The conventional interleaved SMD has multiple pairs of forward delay array (FDA) and backward delay array (BDA) in order to reduce the clock skew. The proposed interleaved SMD requires one FDA and one BDA by changing the position of MUX. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on 0.25 μm two-metal CMOS technology

Keywords

CMOS integrated circuits; clocks; delay circuits; jitter; low-power electronics; power consumption; signal generators; synchronisation; 0.25 μm two-metal CMOS; 0.25 micron; 30% power reduction; 40% area reduction; FDA; MUX; backward delay array; forward delay array; interleaved SMD; interleaved synchronous mirror delay; CMOS technology; Circuit simulation; Clocks; Delay effects; Delay lines; Mirrors; Phase locked loops; Power generation; Random access memory; Synchronous generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010313

Filename

1010313