A highly integrated CMOS image sensor architecture for low voltage applications with deep submicron process

Author

Xu, Chen ; Zhang, WeiQuan ; Ki, Wing-Hung ; Chan, Mansun

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Tech., Kowloon, China

Volume

3

fYear

2002

fDate

2002

Firstpage

699

Lastpage

702

Abstract

In this paper, a design methodology to fabricate a CMOS imaging system in an ultra-low voltage environment with a deep submicron process is presented. The new design methodology is based on a rail-to-rail pixel architecture together with a high dynamic range single-slope analog-to-digital converter (ADC). Correlated doubling sampling (CDS) is built-in in the readout system to suppress both fix pattern noise and kTC noise. An imaging test chip has been fabricated with a TSMC 0.25 μm CMOS process and proved to function at a supply voltage of 1 V or below. Two operation modes are also implemented to tradeoff between high speed and low power operations

Keywords

CMOS image sensors; digital readout; integrated circuit technology; low-power electronics; 0.25 μm CMOS; 0.25 micron; 1 V; CMOS imaging system; TSMC CMOS; correlated doubling sampling; deep submicron process; dynamic range single-slope ADC; fix pattern noise; imaging test chip; rail-to-rail pixel architecture; readout system; ultra-low voltage; voltage below 1 V; CMOS image sensors; CMOS process; CMOS technology; Circuits; Design methodology; Dynamic range; Low voltage; Sampling methods; Sensor arrays; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010320

Filename

1010320