DocumentCode
1803115
Title
An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer
Author
Batten, Robert ; Fiez, Terri S.
Author_Institution
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Volume
3
fYear
2002
fDate
2002
Abstract
An efficient design for a high-speed, high-resolution parallel ΔΣ architecture that is well suited to implementation in a digital CMOS process is presented here. The architecture uses a reduced sample-rate Leslie-Singh channel to enable sharing of one second stage ADC between the parallel channels. This results in reduced power consumption and smaller chip area. The design in this paper achieves 16 bits of resolution, with an 8 times oversampling ratio using a parallel system with four third-order channels and one 9-bit second stage.
Keywords
CMOS digital integrated circuits; delta-sigma modulation; quantisation (signal); 9-bit second stage; chip area; digital CMOS; high-resolution; high-speed delta sigma architecture; power consumption; sample-rate Leslie-Singh channel; third-order channels; Bandwidth; CMOS process; Computer architecture; Demodulation; Design engineering; Digital filters; Energy consumption; Multi-stage noise shaping; Parallel processing; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010324
Filename
1010324
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