A tomography based switched-capacitor measuring circuit with low offset and low temperature drift

Author

Peng, Jia ; Chan, P.K.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

Volume

2

fYear

2004

fDate

18-20 May 2004

Firstpage

1429

Abstract

A new capacitance measuring circuit for an electrical capacitance tomography (ECT) system is proposed. It is based on a switched-capacitor (SC) front-end interface which employs the correlated double sampling (CDS) technique to reduce the DC offset and 1/f noise of the CMOS amplifiers and utilizes a resettable topology to facilitate the high speed charging and discharging operation under a heavy stray capacitance of 150 pF. The SPICE simulation results have validated the circuit, having low offset as well as low temperature drift in a capacitance range of 1 fF to 2 pF using AMS 0.6 μm CMOS process technology with a single 5 V supply.

Keywords

1/f noise; CMOS integrated circuits; amplifiers; capacitance measurement; signal sampling; switched capacitor networks; tomography; 0.6 micron; 1 fF to 2 pF; 1/f noise; 150 pF; 5 V; CMOS amplifiers; ECT; capacitance measurement range; capacitance measuring circuit; correlated double sampling technique; electrical capacitance tomography; high speed charging/discharging operation; low DC offset measuring circuit; low temperature drift measuring circuit; resettable topology; stray capacitance; switched-capacitor front-end interface; tomography imaging system; Capacitance measurement; Circuit noise; Circuit topology; Electric variables measurement; Electrical capacitance tomography; Noise reduction; Operational amplifiers; Sampling methods; Switching circuits; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE

ISSN

1091-5281

Print_ISBN

0-7803-8248-X

Type

conf

DOI

10.1109/IMTC.2004.1351335

Filename

1351335