Title :
On three-dimensional layout of de Bruijn networks
Author :
Yamada, Toshinori ; Ueno, Shuichi
Author_Institution :
Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol., Japan
Abstract :
The de Bruijn networks are well-known as suitable structures for parallel computations such as FFT. This paper shows an efficient 3D VLSI layout of the de Bruijn network with optimal volume and near optimal wire-length. Our layout consists of a number of copies of a single 2D VLSI layout for a subnetwork of the de Bruijn network
Keywords :
VLSI; graph theory; integrated circuit layout; network topology; 3D VLSI layout; de Bruijn networks; near optimal wire-length; optimal volume; parallel computations; Circuits; Computer networks; Concurrent computing; Costs; Decoding; Electronic mail; Very large scale integration; Viterbi algorithm; Volume measurement; Wiring;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010340
