• DocumentCode
    180370
  • Title

    A fast architecture for finding maximum (or minimum) values in a set

  • Author

    Biroli, Andrea Dario Giancarlo ; Juan Chi Wang

  • Author_Institution
    Dipt. di Elettron. e Telecomun., Politec. di Torino, Turin, Italy
  • fYear
    2014
  • fDate
    4-9 May 2014
  • Firstpage
    7565
  • Lastpage
    7569
  • Abstract
    High speed architectures for extracting the best (maximum or minimum) values in a given set and their positions is of high importance in many signal processing applications. For example, the search of the two minimum values is an important part in iterative channel decoders for turbo and low-density-parity-check codes. In this paper, a new architecture is proposed to find the gth best value in an unsorted list of k elements, where the ranking position g can be any integer between 1 and k. The architecture can also be used to find in the assigned set a generic subset of the largest or smallest values. The proposed solution is particularly efficient in terms of hardware complexity and latency when the cardinality of the assigned set k is large and the values are represented on a reduced number of bits n. Synthesis results obtained with a 90-nm CMOS standard cell technology are provided for specific choices of g, k and n. Moreover, the nice properties of regularity and scalability of the proposed architecture are exploited to develop a QCA (quantum cellular automata) based implementation, which achieves lower power consumption or higher speed.
  • Keywords
    cellular automata; channel coding; decoding; parity check codes; quantum theory; signal processing; CMOS standard cell technology; QCA; cardinality; generic subset; hardware complexity; high speed architectures; iterative channel decoders; latency; low-density parity check codes; quantum cellular automata; ranking position; signal processing applications; Clocks; Complexity theory; Computer architecture; Decoding; Microprocessors; Multiplexing; Parity check codes; Application Specific Integrated Circuits; Data processing; digital arithmetic; quantum cellular automata; search methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on
  • Conference_Location
    Florence
  • Type

    conf

  • DOI
    10.1109/ICASSP.2014.6855071
  • Filename
    6855071