DocumentCode :
1804154
Title :
Run-Time Component Relocation in Partially-Reconfigurable FPGAs
Author :
Dumitriu, Victor ; Marcantonio, Dennis ; Kirischian, Lev
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
Volume :
2
fYear :
2009
fDate :
29-31 Aug. 2009
Firstpage :
909
Lastpage :
914
Abstract :
The concept of hardware resource virtualization which was initiated in virtual memory organization has recently expanded towards virtualization of computing resources in partially reconfigurable FPGAs. However, this kind of resource virtualization requires mechanisms for flexible allocation/relocation of components associated with data execution processes. The ability for on-chip component relocation will allow cost efficient multi-task/multi-modal operations in FPGAs by run-time architecture-to-task optimization. On-chip component relocation would also allow hardware fault mitigation and even dynamic self-restoration of FPGA systems. Therefore, the goal of the presented research was to investigate the feasibilityof on-chip component relocation in partially reconfigurable FPGAs. In this proof-of-concept research phase we have analyzed structural requirements of target FPGAs as well as design constraints for the components suitable for on-chiprelocation. As a result, the possibility for run-time relocation of components associated with video-processing applications has been proven. Architectural requirements and component design constraints have been determined. It is shown that the hardware overhead required for performing the relocation procedure is negligible compared to the total amount of FPGA resources. In addition, the component relocation time has been measured according to slot size. It is two orders of magnitude less than the reconfiguration time for the entire target FPGA, which allows quite rapid mode switching or circuit restoration.
Keywords :
field programmable gate arrays; reconfigurable architectures; circuit restoration; data execution processes; field programmable gate array; hardware fault mitigation; hardware resource virtualization; mode switching; multitask-multimodal operations; on-chip component relocation; partially-reconfigurable FPGA; run-time architecture-to-task optimization; run-time component relocation; video processing applications; virtual memory organization; Circuit faults; Cost function; Field programmable gate arrays; Hardware; Resource management; Resource virtualization; Runtime; Size measurement; System-on-a-chip; Time measurement; dynamic reconfiguration; embedded systems; field programmable gate arrays; system design; video processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Science and Engineering, 2009. CSE '09. International Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
978-1-4244-5334-4
Electronic_ISBN :
978-0-7695-3823-5
Type :
conf
DOI :
10.1109/CSE.2009.493
Filename :
5283286
Link To Document :
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