Analysis of the Influence of Layout and Technology Parameters on the Thermal Impedance of GaAs HBT/BiFET Using a Highly-Efficient Tool

Author

Magnani, A. ; d´Alessandro, Vincenzo ; Codecasa, L. ; Zampardi, P.J. ; Moser, B. ; Rinaldi, Niccolo

Author_Institution

Dept. of Electr. Eng. & Inf. Technol., Univ. Federico II, Naples, Italy

fYear

2014

fDate

19-22 Oct. 2014

Firstpage

1

Lastpage

4

Abstract

This work is focused on the analysis of the dynamic thermal behavior of advanced GaAs HBTs, with particular emphasis on BiFET technologies, where pHEMTs are integrated below the conventional bipolar device. A novel highly-efficient tool is employed to determine the influence on the thermal impedance of the key layout and technology features, namely, size of the emitter and base-collector mesa, pHEMT layers, and metallization architecture. The tool relies on the multi-point moment matching algorithm, and allows CPU time and memory storage much lower than those required by commercially-available numerical software packages.

Keywords

III-V semiconductors; gallium arsenide; heterojunction bipolar transistors; high electron mobility transistors; semiconductor device metallisation; BiFET; GaAs; HBT; dynamic thermal behavior; highly efficient tool; metallization architecture; multipoint moment matching algorithm; pHEMT; thermal impedance; Computational modeling; Finite element analysis; Gallium arsenide; Heating; Heterojunction bipolar transistors; Impedance; PHEMTs;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium (CSICs), 2014 IEEE

Conference_Location

La Jolla, CA

Type

conf

DOI

10.1109/CSICS.2014.6978543

Filename

6978543