A digital phase-locked loop with calibrated coarse and stochastic fine TDC

A coarse-fine time-to-digital converter (TDC) is presented with a calibrated course stage followed by a stochastic fine stage. On power-up, calibration algorithm based on a code density test is used to minimize nonlinearities in the coarse TDC. By using a balanced mean method, the number of registers required for calibration algorithm is a reduced by 30%. Based upon the coarse TDC resuls, the appropriate clock signals are multiplexed into a stochastic fine TDC. The TDC is incorporated into a 1.9-2.54 GHz digital phase locked loop (DPLL) in 0.13 μm CMOS. The DPLL consumes a total of 15.2 mW of which 4.4 mW are consumed in the TDC. Measurements show an in-band phase noise of -107 dBc/Hz which is equivalent to 4 ps TDC resolution, approximately an order of magnitude better than an inverter delay in this process technology. The integrated random jitter is 213 fs. The calibration reduces worst-case spurs by 16 dB.