An 8.5–11.5Gbps SONET transceiver with referenceless frequency acquisition

Author

Kocaman, Namik ; Fallahi, Siavash ; Kargar, Mahyar ; Khanpour, Mehdi ; Momtaz, Afshin

fYear

2012

fDate

9-12 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

An 8.5-11.5Gbps SONET transceiver with a referenceless CDR employing an algorithmic frequency acquisition scheme (without using any training sequence) is designed in a 65nm digital CMOS process. A modified digital quadricorrelator frequency detector (M-DQFD) is incorporated into an LC-based VCO coarse tuning adjustment. The transceiver complies with stringent SONET OC-192 jitter requirements. Within a 400μs acquisition time, the RX achieves a high-frequency jitter tolerance of 0.58UIpp at 10mVpp-diff input sensitivity. The TX serial output exhibits a random jitter (RJ) of 205fs (rms). The transceiver occupies 0.97mm² and consumes 141mA at 1.0V.

Keywords

CMOS integrated circuits; SONET; jitter; voltage-controlled oscillators; LC-based VCO coarse tuning adjustment; M-DQFD; SONET OC-192 jitter; SONET transceiver; algorithmic frequency acquisition scheme; bit rate 8.5 Gbit/s to 11.5 Gbit/s; current 141 mA; digital CMOS process; digital quadricorrelator frequency detector; high-frequency jitter tolerance; random jitter; referenceless CDR; referenceless frequency acquisition; size 65 nm; voltage 1.0 V; Calibration; Clocks; Detectors; Jitter; SONET; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2012 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4673-1555-5

Electronic_ISBN

0886-5930

Type

conf

DOI

10.1109/CICC.2012.6330578

Filename

6330578