Title :
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS
Author :
Lu, Yue ; Jung, Kwangmo ; Hidaka, Yasuo ; Alon, Elad
Author_Institution :
Univ. of California, Berkeley, CA, USA
Abstract :
A low-power pre-emphasis voltage mode transmitter architecture with output swing control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only ~10mW from a 1.2V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-tap pre-emphasis, achieving 1pJ/bit energy efficiency.
Keywords :
CMOS integrated circuits; calibration; voltage control; LP CMOS; bit rate 10 Gbit/s; energy efficiency; low power preemphasis voltage mode transmitter architecture; online impedance calibration; output swing control; power 10 mW; preemphasis coefficient control; reconfigurable preemphasis transmitter; size 65 nm; voltage 1.2 V; voltage 400 mV; Decoding; Energy efficiency; Impedance; Logic gates; Regulators; Transmitters; Voltage control;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330581
