An Implementation of the Mean Shift Filter on FPGA

Mean shift algorithm is a procedure which is often used for color image segmentation. Its computational cost, however, is very high, and many techniques for reducing the cost have been researched. This paper describes an approach for real time processing of a mean shift algorithm using an FPGA. In our approach, the image is scanned from top to bottom (or bottom to top), and L lines around the target line are buffered on the FPGA, and the pixels on the target line can be processed efficiently using the buffered pixels. When the pixels are shifted out of the L lines, they are put in queues, and processed afterward. In our circuit, the processing of several pixels is interleaved to hide the delay caused by the long feedback in the mean shift filter. A technique to reduce the number of on-chip memory banks used for storing the L lines is also introduced. The performances of our circuit for 768×512 pixel images is 50 to 130 fps according to the size of the mean shift filter.