Modified CORDIC demodulator implementation for digital IF-sampled receiver

With the expansion of wireless concepts in mobile communications, for example ETTM (electronic tolling and traffic management) and DAB (digital audio broadcasting) receiver, mobile radio designers feel the need to keep the cost of design low while maintaining high performance, and to have high speed digital systems which can perform DSP algorithms to provide immunity to multipath fading problems. A novel approach for VLSI realization of a modified CORDIC (coordinate rotation digital computer) algorithm for a digital IF-sampled receiver is presented. It is intended for an inexpensive realization of a demodulator which is part of the digital IF-sampled digital receiver for AM/FM within a VLSI chip. For high speed carrier phase synchronization digital systems, this hardware design can be used to acquire the phase information for further carrier phase processing. The modified CORDIC offers several advantages. First, it has no initial start up. Second, scaling factors can be computed at the end of the CORDIC iterations. The modified CORDIC is proposed to maintain precision with less hardware complexity. Overall, the algorithm is computationally efficient and conceptually simple. It is implemented in VHDL (very high speed integrated circuit hardware description language)