A new VLSI architecture of Reed Solomon decoder with erasure function

A new VLSI architecture of Reed Solomon decoder with erasure function and using a modified Euclid´s algorithm to solve the key equation is presented. Its correction ability is 20 bytes/block. The block length is variable (from 96 bytes to 255 bytes). Hardware complexity is dependent only on 2t (number of parity check bytes). Due to the modified Euclid´s algorithm, the hardware required for solving the RS code´s key equation is reduced and the control circuitry simplified, thus this architecture is suitable for VLSI implementation. The decoder is reduced to a three stages pipelined structure. Its algorithms were simulated with C language, and over 6 million pattern were tested without mistake. The algorithm state machine (ASM) and architecture were verified with the Verilog description language, and over twelve thousand patterns were tested without mistake