Title :
A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration
Author :
Kim, Seungjin ; Lee, In-Young ; Kim, Joo-Myoung ; Lee, Sang-Gug
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
A high-speed and low-power adaptable period SAR-based DAC gain calibration is presented for DSM quantization noise suppression, which completes within 10μs while dissipating 0.2mW. The proposed calibration scheme is applied to the fractional-N type frequency synthesizer which adopts an 8-bit noise-cancelling DAC. The frequency synthesizer has a range of 48 to 900 MHz, consumes 11mA from 1.2-V supply and occupies 1.5 × 1.4 mm2 in 0.13μm CMOS process. The measurement shows more than 30-dB quantization noise suppression at a 877MHz oscillation frequency which results in the phase noise of -100.7dBc/Hz and -134.5dBc/Hz at 100-kHz and 1.25-MHz offset frequencies respectively.
Keywords :
CMOS integrated circuits; delta-sigma modulation; frequency synthesizers; interference suppression; low-power electronics; quantisation (signal); CMOS process; DSM quantization noise suppression; calibration scheme; fractional-N type frequency synthesizer; high-speed low-power adaptable period SAR-based DAC gain calibration; noise-cancelling DAC; oscillation frequency; quantization noise cancelling fractional-N type ΔΣ frequency synthesizer; Calibration; Computer architecture; Correlation; Frequency synthesizers; Noise; Quantization; Timing;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330592