A reduced multistage architecture for ATM networks

A novel communication switch architecture for ATM (asynchronous transfer mode) networks is presented. The speed of the proposed switch architecture is clock-rate-dependent. This architecture has a modular structure and provides a pipeline activity which reduces head-of-line blocking. As a result of using this architecture, the number of stages required is one half the number of stages used in switches today. This results in a reduction of delay to a maximum of 100% for the ideal case and to 20% on average and a reduction in throughput delay of 25% for the nonideal case when compared with a Banyan network. Because of its high degree of modularity, the architecture can be easily implemented using VLSI techniques