Title :
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions
Author :
López, J.A. ; Doménech, G. ; Ruiz, R. ; Kazmierski, T.J.
Author_Institution :
Dipt. Electronica y Tec. de Computadoras, Univ. Politecnica de Cartagena, Spain
Abstract :
This contribution presents a VHDL-AMS model for a building block present in a multi-channel neural network based on the adaptive resonance theory, and its automated synthesis using a VHDL-AMS to HSPICE netlist translator. This building block shows continuous dynamic behavior, and it is complex enough to check the functionality of our translator. Both simulations, the behavioral high-level one based on the VHDL-AMS model and the structural one based on an automatically synthesized SPICE description, have verified the matching between the SPICE netlist synthesized against its VHDL-AMS model.
Keywords :
ART neural nets; SPICE; hardware description languages; high level synthesis; integrated circuit design; integrated circuit modelling; mixed analogue-digital integrated circuits; ART-based neural network hardware building blocks; SPICE netlist; VHDL-AMS descriptions; VHDL-AMS model; VHDL-AMS to HSPICE netlist translator; adaptive resonance theory; analog mixed-signal; automated high level synthesis; automatically synthesized SPICE description; behavioral high-level simulation; building block complexity; continuous dynamic behavior building block; multi-channel neural networks; structural simulation; translator functionality; Circuit simulation; Computer networks; Electronic design automation and methodology; High level synthesis; Intelligent networks; Network synthesis; Neural network hardware; Neural networks; Resonance; SPICE;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010392