DocumentCode :
1804636
Title :
Leros: A Tiny Microcontroller for FPGAs
Author :
Schoeberl, Martin
Author_Institution :
Dept. of Inf. & Math. Modeling, Tech. Univ. of Denmark, Lyngby, Denmark
fYear :
2011
fDate :
5-7 Sept. 2011
Firstpage :
10
Lastpage :
14
Abstract :
Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive soft core for many-core research with low-cost FPGAs.
Keywords :
field programmable gate arrays; microcontrollers; system-on-chip; FPGA; Leros; auxiliary functions; intelligent peripheral device; logic cells; microcontroller; on-chip memory block; pipelined accumulator processor; soft core; system-on-chip design; word length 16 bit; Clocks; Delta modulation; Field programmable gate arrays; Microcontrollers; Pipelines; Registers; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2011 International Conference on
Conference_Location :
Chania
Print_ISBN :
978-1-4577-1484-9
Electronic_ISBN :
978-0-7695-4529-5
Type :
conf
DOI :
10.1109/FPL.2011.13
Filename :
6044776
Link To Document :
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