Title :
Low power register file architecture for application specific DSPs
Author :
Mueller, M. ; Wortmann, A. ; Simon, S. ; Wolter, S. ; Buch, S. ; Wroblewski, M. ; Nossek, J.A.
Author_Institution :
Infineon Technol. AG, Germany
Abstract :
In this paper, an architecture for register files suited for synthesizable DSP cores is proposed. The principal focus is on the implementation of DSP algorithms with several identical channels, used in e.g. stereo audio, filter banks or network IC implementations. Nevertheless, it is shown that the result of this work can be extended to many single channel applications by formal assignment of operations to several channels. The new register file architecture is especially suited for a standard semi-custom design flow based on common hardware description languages in conjunction with commercial synthesis tools. The level of abstraction used here is the register-transfer level (RTL). Due to the proposed register file architecture, the power dissipation of our application is reduced by 30% compared to the conventional implementation.
Keywords :
application specific integrated circuits; digital signal processing chips; hardware description languages; integrated circuit design; integrated circuit modelling; logic CAD; low-power electronics; parallel architectures; ASIC; DSP core synthesis; RTL; application specific DSP; filter banks; hardware description languages; identical channel DSP algorithms; low power register file architecture; network IC implementations; operation formal assignment; power dissipation reduction; register-transfer level; semi-custom design flow; single channel applications; stereo audio; synthesis tools; Circuits; Clocks; Delay; Digital signal processing; Hardware design languages; Interleaved codes; Network synthesis; Registers; Signal synthesis; Timing;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010395
