Low power register file architecture for application specific DSPs

In this paper, an architecture for register files suited for synthesizable DSP cores is proposed. The principal focus is on the implementation of DSP algorithms with several identical channels, used in e.g. stereo audio, filter banks or network IC implementations. Nevertheless, it is shown that the result of this work can be extended to many single channel applications by formal assignment of operations to several channels. The new register file architecture is especially suited for a standard semi-custom design flow based on common hardware description languages in conjunction with commercial synthesis tools. The level of abstraction used here is the register-transfer level (RTL). Due to the proposed register file architecture, the power dissipation of our application is reduced by 30% compared to the conventional implementation.