A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs

The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the next wave of consumer electronics products. However, the benefits of such an integration technology have not been sufficiently explored yet. In this paper, we introduce a novel 3-D architecture, as well as the software supporting tools for exploring and evaluating application mapping onto 3-D FPGAs, where logic and I/O resources are assigned to different layers. Experimental results shown that such a 3-D architecture is suitable especially for communication intensive applications, since a device with two layers achieves delay reduction, as compared to conventional 2-D FPGAs up to 87% without any overhead in power dissipation.