On test data compaction using linear cycle registers

Compact testing (testing where data compression is employed to reduce a size of test response sequences and reference data) is widely used in the modern automated test instrumentation systems aimed at digital and mixed-signal devices. Cycle shift registers are among the most effective data compactors. They provide low hardware overhead, high operation speed and good fault coverage. The aim of this paper is to investigate single-input and multiple-input cycle registers and to derive the most general and non-recurrent analytical description of their operation. The description is then deployed for test reference data calculation. And it can also be used as a tool for error diagnosis. Another goal of the paper is to develop and research an alternative equivalent architecture for a multiple-channel cycle register allowing to produce detail error coverage analysis of this data compactor for an arbitrary bit-error multiplicity and the error configuration.