DocumentCode
1804852
Title
A 180nm CMOS image sensor with on-chip optoelectronic image compression
Author
Wang, Albert ; Sivaramakrishnan, Sriram ; Molnar, Alyosha
Author_Institution
Cornell Univ., Ithaca, NY, USA
fYear
2012
fDate
9-12 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
We demonstrate an image sensor which directly acquires images in a compressed format. The sensor uses diffractive optical structures integrated in the CMOS back-end layer stack to compute a low-order 2D spatial Gabor transform on visual scenes. As this computation occurs in the optical domain, the readout back-end uses the transform outputs to implement the subsequent image digitization and compression simultaneously. Implemented in a 180nm logic CMOS process, the image sensor uses a 384×384 array of complementary angle-sensitive pixel pairs, consumes 2mW at a frame rate of 15fps, and achieves a 10:1 compression ratio on test images.
Keywords
CMOS image sensors; data compression; image coding; integrated optoelectronics; logic circuits; transforms; CMOS image sensor; CMOS readout back-end layer stack; complementary angle-sensitive pixel pair; image digitization; image testing; logic CMOS processing; low-order 2D spatial Gabor transform; on-chip optoelectronic image compression; optical domain structure; power 2 mW; size 180 nm; visual scene; Diffraction; Diffraction gratings; Image coding; Image sensors; Optical imaging; Optical sensors; Transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4673-1555-5
Electronic_ISBN
0886-5930
Type
conf
DOI
10.1109/CICC.2012.6330604
Filename
6330604
Link To Document