A programmable simulator for analyzing the block data flow architecture

Author

Alexandre, Sean ; Alexander, Winser ; Reeves, Douglas S.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

1994

fDate

31 Jan-2 Feb 1994

Firstpage

399

Lastpage

400

Abstract

A programmable simulator has been developed for analyzing the performance of a class of parallel computers. The simulator provides detailed information about the timing, resource usage, and output results for an algorithm executing on the parallel computer. A user specifies the configuration and performance characteristics of the computer to be simulated. The user also describes the algorithm to be executed on the computer. The use of the simulator for QR factorization is briefly described and the results are presented. Our approach is compared with other simulation methods

Keywords

parallel machines; performance evaluation; system monitoring; virtual machines; QR factorization; block data flow architecture; configuration; parallel computers; performance characteristics; programmable simulator; resource usage; simulation methods; timing; Analytical models; Communication system control; Computational modeling; Computer simulation; Concurrent computing; Data analysis; Discrete event simulation; Signal processing algorithms; Timing; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1994., MASCOTS '94., Proceedings of the Second International Workshop on

Conference_Location

Durham, NC

Print_ISBN

0-8186-5292-6

Type

conf

DOI

10.1109/MASCOT.1994.284391

Filename

284391