Title :
Hardware Support for Broadcast and Reduce in MPSoC
Author :
Peng, Yuanxi ; Saldaña, Manuel ; Chow, Paul
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
MPI has been used as a parallel programming model for supercomputers and clusters but also in Multiprocessor System-on-Chip. One component of MPI is collective communication and its performance is key for parallel applications to achieve good speedups. Considerable research has been done to optimize such communication by improving the MPI library algorithms. However, these optimizations are focused on the processing nodes (end-points in a network) rather than on the network itself. In this paper, we target a Network-on-Chip (NoC) and modify it to provide hardware support for broadcast and reduce operations for the ArchES-MPI library. This library is a subset implementation of the MPI standard targeting embedded processors and hardware accelerators implemented in FPGAs. The experimental results show that for a system with 24 embedded processors, the broadcast and reduce operations improved up to 11.4-fold and 22-fold, respectively. Higher benefits are expected for larger systems at the expense of a modest increase resource utilization.
Keywords :
broadcasting; embedded systems; message passing; network-on-chip; ArchES-MPI library; FPGA; MPI library algorithm; MPSoC; Network-on-Chip; broadcast operation; embedded processors; hardware accelerator; hardware support; multiprocessor system-on-chip; parallel programming model; reduce operation; resource utilization; Adders; Arrays; Clustering algorithms; Field programmable gate arrays; Hardware; Program processors; Protocols; FPGA; MPI; Multiprocessor; Network-on-Chip; Parallel Computing;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2011 International Conference on
Conference_Location :
Chania
Print_ISBN :
978-1-4577-1484-9
Electronic_ISBN :
978-0-7695-4529-5
DOI :
10.1109/FPL.2011.34
