Extremely thin SOI for system-on-chip applications

Author

Khakifirooz, A. ; Cheng, K. ; Liu, Q. ; Nagumo, T. ; Loubet, N. ; Reznicek, A. ; Kuss, J. ; Gimbert, J. ; Sreenivasan, R. ; Vinet, M. ; Grenouillet, L. ; Le Tiec, Y. ; Wacquez, R. ; Ren, Z. ; Cai, J. ; Shahrjerdi, D. ; Kulkarni, P. ; Ponoth, S. ; Luning,

Author_Institution

IBM, Albany, NY, USA

fYear

2012

fDate

9-12 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of V_T tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.

Keywords

CMOS integrated circuits; silicon-on-insulator; system-on-chip; CMOS scaling; ETSOI technology; SRAM; VT tuning; analog devices; backbias; embedded memory; extremely thin SOI; low-power high-performance logic; main device characteristics; passive devices; system-on-chip applications; CMOS integrated circuits; Doping; FinFETs; Junctions; Logic gates; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2012 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4673-1555-5

Electronic_ISBN

0886-5930

Type

conf

DOI

10.1109/CICC.2012.6330618

Filename

6330618