Wire sizing optimization for buffered global interconnects

This paper presents a novel methodology to achieve the optimal wire sizing of buffered global interconnects. Based on the model of optimal repeater insertion, the impact of the line width and spacing on performance, such as delay, power dissipation and area, is investigated. The power-delay product is therefore defined as a figure of merit (FOM). An analytical expression for the optimal line width is presented. The effects of the weight factor and constrained coefficient on performance are investigated and some useful guidelines for wire sizing of global interconnects are proposed.