• DocumentCode
    1805408
  • Title

    Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures

  • Author

    Konoura, Hiroaki ; Mitsuyama, Yukio ; Hashimoto, Masanori ; Onoye, Takao

  • Author_Institution
    Dept. Inf. Syst. Eng., Osaka Univ., Osaka, Japan
  • fYear
    2011
  • fDate
    5-7 Sept. 2011
  • Firstpage
    189
  • Lastpage
    194
  • Abstract
    Fault avoidance methods on dynamically reconfigurable devices have been proposed to extend device life-time, while their quantitative comparison has not been sufficiently presented. This paper shows results of quantitative life-time evaluation by simulating fault avoidance procedures of representative five methods under the same conditions of wear-out scenario, application and device architecture. Experimental results reveal 1) MTTF is highly correlated with the number of avoided faults, 2) there is the efficiency difference of spare usage in five fault avoidance methods, and 3) spares should be prevented from wear-out not to spoil life-time enhancement.
  • Keywords
    fault tolerance; life testing; reconfigurable architectures; semiconductor device reliability; MTTF; device architecture; device life-time evaluation; dynamically reconfigurable architecture; fault avoidance method; reliability enhancement; spare usage; Aging; Circuit faults; Fault tolerance; Fault tolerant systems; Finite impulse response filter; Switches; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2011 International Conference on
  • Conference_Location
    Chania
  • Print_ISBN
    978-1-4577-1484-9
  • Electronic_ISBN
    978-0-7695-4529-5
  • Type

    conf

  • DOI
    10.1109/FPL.2011.108
  • Filename
    6044807