A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode

A gain cell embedded DRAM (eDRAM) in a 65nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local voltage sense amplifiers. A low-overhead dual-row access mode improves the worst-case cell retention time by 3X, minimizing refresh power at times when only a fraction of the entire memory is utilized. Measurement results from a 64kb eDRAM test chip in 65nm CMOS demonstrate the effectiveness of the proposed circuit techniques.