Title :
Design Methods for Multiple-Valued Input Address Generators
Author_Institution :
Kyushu Institute of Technology, Japan
Abstract :
A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.
Keywords :
Circuit testing; Computer science; Databases; Design methodology; Dictionaries; Fuzzy logic; Internet; Logic design; Logic testing; Programmable logic arrays;
Conference_Titel :
Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on
Print_ISBN :
0-7695-2532-6
DOI :
10.1109/ISMVL.2006.17
