Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems

Standby power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× standby leakage reduction at V_DD=4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.