A scalable sorting architecture based on maskable WTA/MAX circuit

Sorting plays an important role in data and digital signal/image processing. We propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort an arbitrary N items of data with a simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, the proposed sorting system can be expanded easily by a simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. A modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of our proposed sorter can be easily augmented to 16-bit or 32-bit. The sorter chip has been manufactured by a TSMC 0.35 μm 1P4M process with a 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.