Spiral and solenoidal inductor structures on silicon using Cu-damascene interconnects

Author

Edelstein, Daniel C. ; Burghartz, Joachim N.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1998

fDate

1-3 Jun 1998

Firstpage

18

Lastpage

20

Abstract

Spiral, multilevel spiral, and lateral solenoidal inductor structures are fabricated on silicon substrates using a Cu-damascene VLSI interconnect technology with a 4 μm-thick Cu top layer. Some chips are mounted on quartz substrates to suppress substrate losses. An 80-nH, 16-turn spiral inductor on quartz has a Q of 20, the highest recorded value to date for an integrated inductor of this size

Keywords

Q-factor; VLSI; copper; inductors; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; losses; 4 micron; Cu; Cu top layer; Cu-damascene VLSI interconnect technology; Cu-damascene interconnects; inductor Q value; integrated inductor; lateral solenoidal inductor structures; multilevel spiral inductor structures; quartz substrates; silicon substrates; solenoidal inductor structures; spiral inductor; spiral inductor structures; substrate loss suppression; Coils; Digital signal processing chips; Frequency; Inductors; Influenza; Integrated circuit interconnections; Silicon; Spirals; Transceivers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704740

Filename

704740