A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware

Author

Akin, Abdulkadir ; Ulusel, Onur Can ; Ozcan, Tevfik Zafer ; Sayilar, Gokhan ; Hamzaoglu, Ilker

Author_Institution

Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey

fYear

2011

fDate

5-7 Sept. 2011

Firstpage

269

Lastpage

272

Abstract

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. Therefore, in this paper, we propose comparison prediction (CP) technique for reducing the power consumption of block matching (BM) ME hardware. CP technique reduces the power consumption of absolute difference operations performed by BM ME hardware. CP technique can easily be used in all BM ME hardware. In this paper, we applied it to a 256 processing element fixed block size ME hardware implementing full search algorithm. It reduced the average dynamic power consumption of this ME hardware by 2.2% with no Peak Signal-to-Noise Ratio (PSNR) loss and by 9.3% with 0.04% PSNR loss on a XC2VP30-7 FPGA.

Keywords

data compression; field programmable gate arrays; image enhancement; motion estimation; prediction theory; video coding; XC2VP30-7 FPGA; block matching motion estimation hardware; comparison prediction technique; full search algorithm; power consumption reduction; power reduction technique; video compression system; video enhancement system; Field programmable gate arrays; Hardware; Motion estimation; PSNR; Power demand; Prediction algorithms; Registers; FPGA; block matching; hardware implementation; motion estimation; power reduction;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications (FPL), 2011 International Conference on

Conference_Location

Chania

Print_ISBN

978-1-4577-1484-9

Electronic_ISBN

978-0-7695-4529-5

Type

conf

DOI

10.1109/FPL.2011.54

Filename

6044827