Title :
A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint
Author :
Sulaiman, Mohd S.
Author_Institution :
Fac. of Eng., Multimedia Univ., Selangor, Malaysia
Abstract :
A heuristic algorithm for optimized clock network design is presented. The algorithms for optimization of clock skew, delay, and power considering slew rate constraint for a balanced IC clock tree are implemented using a modified method of cautious approach. Algorithms developed are verified with the model of a real chip, i.e. post layout model of an FPGA chip. HSpice simulations at 115°C, with CMOS 0.35 μm models and parameters show a 60% reduction in the clock slew rate and a 23% improvement in the power dissipation when compared to the results of the initial, unoptimized chip.
Keywords :
CMOS digital integrated circuits; field programmable gate arrays; timing circuits; 0.35 micron; 115 degC; CMOS model; FPGA chip; HSpice simulations; balanced IC clock tree; balanced clock network design algorithm; clock delay; clock skew; field programmable gate array chip; power dissipation; slew rate constraint; Algorithm design and analysis; Clocks; Constraint optimization; Delay effects; Design engineering; Design optimization; Energy consumption; Frequency; Power dissipation; Semiconductor device modeling;
Conference_Titel :
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN :
0-7803-7578-5
DOI :
10.1109/SMELEC.2002.1217776
