Interconnect model at multi-GHz frequencies incorporating inductance effect

The interconnect delay is the dominant factor in determination of speed of synchronous systems. This delay has been modeled as RC component in available EDA tools. This has caused over design of clock trees by 20-30% to account for this inaccuracy. In this paper, we model the interconnect as RLC for systems running at multi-GHz which affect the system-level timing. A static extraction analysis method is detailed and various improvement criteria are discussed. Utilizing this analysis, more accurate interconnect delay models is obtained. These models, in turn, provide more accurate analysis for characterizing circuits.