Fast RTL Power Estimation for FPGA Designs

This paper presents a fast method of performing RTL power estimation. A context-based, activity propagation engine is used to analyze specific structures identified in the RTL. This estimator was integrated into an FPGA tool flow to provide near instant feedback on expected power dissipation. To fully validate our methodology, a large benchmark suite of designs was used to target three different FPGA families. Our results were compared against a commercial gate-level power estimator. Results show a high level of accuracy (total power average error within 8.1% of a post-route analysis) while achieving a median run-time of 1.84 sec., more than 1000 times faster than a complete place and route flow.