Title :
The feasibility of using compression to increase memory system performance
Author :
Wang, Jenlong ; Quong, Russell W.
Author_Institution :
Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
31 Jan-2 Feb 1994
Abstract :
We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression effectively increases the memory size and the line size reducing the miss rate at the expense of increased access latency due to decompression delays. We analytically evaluate the impact of compression on the average memory access time for various memory systems and compression approaches. Our results show the benefit of using compression is sensitive to the miss rates and miss penalties at the point of compression and to a lesser extent the amount of compression possible. For high performance workstations of today, compression already shows promise; as miss penalties increase in future, compression will only become more feasible
Keywords :
buffer storage; data compression; fault tolerant computing; performance evaluation; storage management; cache; compression; data compression; decompression delays; high performance workstations; instruction compression; line size; memory access time; memory system performance; miss rate; multilevel memory hierarchy; Data compression; Decoding; Delay effects; Engines; Hardware; Pressing; Runtime; System performance; Workstations;
Conference_Titel :
Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1994., MASCOTS '94., Proceedings of the Second International Workshop on
Conference_Location :
Durham, NC
Print_ISBN :
0-8186-5292-6
DOI :
10.1109/MASCOT.1994.284438