Low power implementation of high throughput FIR filters

The paper presents a scheme for low power implementation of high throughput FIR filters. The scheme incorporates a new architecture, which consists of multiple parallel processing units. Each unit processes data and coefficient inputs under different representation schemes in order to minimise switching activity at multiplier inputs within a framework in which coefficients are allocated to groups associated with specific processing units prior to filtering. The allocation procedure considers both inter and intra group correlation. The paper describes the scheme and the filtering architecture with a number of filtering structures, and provides results which show up to 56% savings in power.