Title :
New LDMOS transistor based on 0.6 μ CMOS technology for power IC applications
Author :
Hussain, S. ; Holland, P.M. ; Starke, T. ; Igic, P.M. ; Mawby, P.A.
Author_Institution :
Fac. of Eng., Univ. of Wales Swansea, UK
Abstract :
New LDMOSFET device based on 0.6 microns CMOS technology (X-Fab Plymouth, UK) is presented in this paper. The process is based on p-(substrate)/p-(epi) layers, layer thicknesses and dopings being standard for this type of technology. The optimised device has a 75 V breakdown voltage.
Keywords :
CMOS integrated circuits; power MOSFET; semiconductor device breakdown; semiconductor epitaxial layers; 0.6 micron; 75 V; CMOS technology; LDMOS transistor; breakdown voltage; optimised device; p-substrate/p-epilayers; power IC applications; Breakdown voltage; CMOS process; CMOS technology; Doping; Energy management; Integrated circuit technology; MOSFET circuits; Power MOSFET; Power integrated circuits; Silicon;
Conference_Titel :
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN :
0-7803-7578-5
DOI :
10.1109/SMELEC.2002.1217798
